Various computer system architectures have employed a number of approaches to attempt to efficiently transfer blocks of data across busses and between devices (including memory devices, I/O devices, etc.) within a computer system. One of the simplest approaches has been to allow the. CPU (central processing unit) to read a block of data from one device and then write the block of data to another device. However, this task is often regarded as a task better suited to being delegated to other alternative mechanisms so that the CPU may be more fully devoted to carrying out more complex calculations and other computational tasks.
One widely used alternative mechanism is the addition of a DMA (direct memory access) controller to such a computer system to take over the moving of blocks of data between the system memory of the computer system and other devices. Typically, such DMA controllers are programmed to carry out a specific transfer of a block of data by the CPU writing the parameters of the transfer directly into registers within the DMA controller. Then, as the transfer of a block of data is carried out, the CPU is typically programmed to poll one or more of the registers within the DMA controller to query the status of the transfer.
However, use of such a DMA controller has drawbacks. Although the CPU is relieved of the burden of actually carrying out the transfer of a block of data, having the CPU poll registers within the DMA controller to query the status of the transfer is still often considered inefficient. Also, in many implementations of computer systems, write operations carried out by the CPU to program registers within the DMA controller and read operations carried out by the CPU to query status from a register within the DMA controller may take more time than is deemed desirable.
Another widely used alternative mechanism is the incorporation of bus mastering capabilities into various I/O devices within a computer system so that the devices, themselves, are able to autonomously carry out the transfer of blocks of data. Typically, such transfers are programmed to take place by the CPU writing the parameters of the transfer directly into registers within such a bus mastering device. Then as the transfer of a block of data is carried out, the CPU polls one or more of the registers within the bus mastering device to query the status of the transfer.
However, such a use of a bus mastering device has drawbacks. Although the CPU is relieved of the burden of actually carrying out the transfer of a block of data, write operations carried out by the CPU to program registers within the DMA controller and read operations carried out by the CPU to query status from registers within the DMA controller may take more time than is deemed desirable. Also, read operations carried out by a bus mastering device, especially to read a block of data from system memory, may also take more time than is deemed desirable.